There are different data types in systemverilog that can be used like the following:
What is the difference between bit7:0 sig1; and byte sig2; What is the difference between program block and module? What is final block? How to implement always block logic in program block? What is the difference between fork/joins, fork/joinnone fork/joinany? What is the use of modports? Write a clock generator without using always.
How does the three of them differ?
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![Bits Bits](http://asicguru.com/media/asicguru/images/SystemVerilogDataTypesOverview.png)
5 Answers
reg
and wire
were the original types. Wires are constantly assigned and regs are evaluated at particular points, the advantage here is for the simulator to make optimisations.A common mistake when learning Verilog is to assume the a reg type implies a register in hardware. The earlier optimisation for the simulator can be done through the context of its usage.
This introduces
logic
which can be used in place of wire and reg.The type
bit
and byte
have also been created that can only hold 2 states 0 or 1 no x or z. byte
implies bit [7:0]
. Using these types offers a small speed improvement but I would recommend not using them in RTL as your verification may miss uninitialized values or critical resets.The usage of
bit
and byte
would be more common in testbench components, but can lead to issues in case of having to drive x's to stimulate data corruption and recovery.Update
At the time of writing I was under the impression that
logic
could not be used for tristate, I am unable to find the original paper that I based this on. Until further updates, comments or edits, I revoke my assertion that logic can not be used to create tri-state lines.The
tri
type has been added, for explicitly defining a tri-state line. It is based on the properties of a wire
, logic
is based on the properties of a reg
.If you no longer have to support backwards compatibility Verilog then I would recommend switching to using
MorganMorganlogic
and tri
. Using logic
aids re-factoring and and tri
reflects the design intent of a tristate line.16.2k5 gold badges47 silver badges72 bronze badges
- The choice of the name
reg
turned out to be a mistake, because the existence of registers is instead inferred based on how assignments are performed. Due to this, use ofreg
is essentially deprecated in favor oflogic
, which is actually the same type. logic
is a 1-bit, 4-state data typebit
is a 1-bit, 2-state data type which may simulate faster thanlogic
- If a
logic
is also declared as awire
, it has the additional capability of supporting multiple drivers. Note that by defaultwire
is equivalent towire logic
. - In general, the 'nets' (such as
wire
andtri
) are most suitable for designing communication buses.
Practically speaking, for RTL it usually doesn't matter whether you declare with
reg
, or logic
, or wire
. However, if you have to make an explicit declaration of a 4-state type (as opposed to when you don't), you should typically choose logic
since that is what is intended by the language.Related articles:
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nobarnobar28.5k10 gold badges92 silver badges104 bronze badges
As I'm unable to add a comment I've to write what looks like a new answer but isn't. Sigh!
@e19293001, @Morgan,
logic
defines a 4-state variable unlike bit
, and hence a logic
variable can be used to store 1'bz
so the following code is valid and compiles:But I agree that to reflect the design intent
tri
should be used instead of logic
in these cases (although I must say I don't see people using tri
instead of logic
/wire
too often).PadduPaddu
Logic data type doesn't permit multiple driver. The last assignment wins in case of multiple assignment .Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.
Prasanjit BenganiPrasanjit Bengani
reg and logic are exactly the same. These data types appear inside the always or initial blocks and store values i.e. always @(a) b <= a;, the reg b gets evaluated only when 'a' changes but otherwise it simply stores the value it has been assigned last.
wire are just simply connections and need to continuously driven. I agree that they can behave identical as @Morgan mentioned, but they can be imagined as a piece of hard wire, the value of which changes only the value at the other end or the source changes.
Vinayak BhatVinayak Bhat
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$begingroup$What is the difference between
>>
and >>>
in verilog/system verilog? I know that tests for only 1 and 0, while tests for 1, 0, X, Z. So how is that similar to the shift operator?dautdaut
$endgroup$2 Answers
$begingroup$It is not similar to /, if the left hand operand is signed then
>>>
performs sign extension.Result:
Example on EDA Playground.
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pre_randomizepre_randomize
$endgroup$$begingroup$According to IEEE1800-2012
>>
is a binary logical shift, while >>>
is a binary arithmetic shift.Basically, arithmetic shift uses context to determine the fill bits, so:
- arithmetic right shift (
>>>
) - shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero, - arithmetic left shift (
<<<
) - shift left specified number of bits, fill with zero.
On the other hand, logical shift (
<<
, >>
) always fill the vacated bit positions with zeroes.For example:
Qiu![Bit Bit](/uploads/1/2/4/9/124932980/460394488.jpg)
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$endgroup$